Manufacturing Conferences & Events in California — 2026
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This 2026 California manufacturing calendar covers industry forums, networking meetings, investment workshops, and technical conferences across the San Francisco Bay Area and Los Angeles. Attendees typically include semiconductor and electronics professionals, manufacturing innovators, investors, utilities and regulatory stakeholders, and representatives of industry organizations.
Recurring themes include semiconductor materials and electron-device technology, Silicon Valley business opportunities, additive manufacturing, industry networking, and public investment planning. The listed gatherings reflect both specialized technical exchange and broader coordination among companies, professional societies, innovation institutes, and California’s public utilities regulator.
Highlighted events
OCT
15
THU
SEMI (Semiconductor Equipment and Materials International) · San Francisco (San Francisco Bay Area), CA
Robotics & Automation · SemiconductorsThis FOA members-only program includes a general meeting, semiconductor manufacturing case studies, and a networking lunch. Topics include Scaling Agentic AI in Semiconductor Manufacturing at Intel; Implementing a Single Source for Recipe Selection and Management for Greater Quality & Efficiency at Onsemi Nampa, ID; From Static Capacity Moder to Dynamic Capacity Planning: Depolyment Case Study at Diodes; and the AI Technicians Readiness Survey from SEMI and NextFlex. Surya Iyer, President and Board Member, Polar Semiconductor, and Geno Fallico, Vice President of Chandler Fab Operations, NXP Semiconductors, are named presenters.
OCT
27
TUE
–
OCT
29
THU
America Makes TRX Fall
NotableAmerica Makes (National Additive Manufacturing Innovation Institute) · Redondo Beach (Los Angeles), CA
Aerospace & Defense · Heavy Machinery & Equipment · Robotics & AutomationThe Technical Review & Exchange showcases America Makes’ contracted research and development portfolio for additive manufacturing and convenes project engineers, managers, partners, and stakeholders from industry, academia, government, and economic development agencies. The program covers trusted metal additive manufacturing; 3D-printed molds and cores for sand casting; aluminum, nickel superalloy, and Ti-6Al-4V material datasets; sustainable additive manufacturing operations; statistical testing for powder-supplier equivalency; recycling of circular additive powders; aluminum manufacturing maturation; additive manufacturing qualification and interoperability; silicon carbide production; data-driven qualification; airworthiness; and additive manufacturing for space, aircraft, rocket engines, thermal-management systems, high-temperature coatings, C-103 components, and future vertical lift. Featured presentations include “Space Park History and AM in Space,” “Production at Speed: Additively Manufactured Ceraprint™ Silicon Carbide at Northrop Grumman AOX,” and “AM in Manned and Unmanned Airplanes.”
DEC
12
SAT
–
DEC
16
WED
IEEE International Electron Devices Meeting (IEDM) · San Francisco (San Francisco Bay Area), CA
Electronics · SemiconductorsThe program covers semiconductor and electronic device technology, design, manufacturing, physics, modeling, and emerging computing architectures. It includes keynote presentations, technical paper sessions, tutorials, short courses, industry panels, and exhibits. Keynotes address “AI Driven Semiconductor Paradigm Shift: Optimizing the Semiconductor Industry from Device Scaling to System Integration,” “Driving AI Memory Innovation: From Device Technology to AI Memory Platform,” and “Technology Trends in the IDM Semiconductor Business.” Tutorials cover transistor evolution from planar devices to nanosheets and beyond; chiplets, heterogeneous integration, and 3D stacking; memory technologies and system co-optimization in the AI era; AI in physics-based semiconductor modeling; diverse memory technologies for adaptive computing; and advanced optical devices and wafer-scale assembly for co-packaged optics and optical I/O. The short-course program addresses distributed network design for AI, angstrom-era logic scaling, edge-device performance and design-technology/system-technology co-optimization, atomic-layer processing, advanced-packaging reliability, cryogenic electronics, memory-centric computing, HBM, oxide-semiconductor-channel DRAM, NAND scaling, spintronics, and chiplet and advanced-packaging technologies for AI and HPC systems.
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