Manufacturing Conferences & Events in San Francisco Bay Area, CA
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This calendar covers manufacturing gatherings in the San Francisco Bay Area, including semiconductor networking meetings, breakfast forums, investment workshops, design and technology conferences, and industry summits. Attendees typically include semiconductor professionals, engineers, researchers, investors, business leaders, and public-sector participants.
Recurring themes include semiconductor opportunities and investment, solid-state circuits, electron devices, design, equipment and materials, and utility-related planning. The sample also reflects a mix of professional networking, technical exchange, research-oriented programming, and public utility proceedings, with events organized by industry associations, conference producers, IEEE groups, a business chamber, and a California state commission.
Highlighted events
OCT
15
THU
SEMI (Semiconductor Equipment and Materials International) · San Francisco (San Francisco Bay Area), CA
Robotics & Automation · SemiconductorsThis FOA members-only program includes a general meeting, semiconductor manufacturing case studies, and a networking lunch. Topics include Scaling Agentic AI in Semiconductor Manufacturing at Intel; Implementing a Single Source for Recipe Selection and Management for Greater Quality & Efficiency at Onsemi Nampa, ID; From Static Capacity Moder to Dynamic Capacity Planning: Depolyment Case Study at Diodes; and the AI Technicians Readiness Survey from SEMI and NextFlex. Surya Iyer, President and Board Member, Polar Semiconductor, and Geno Fallico, Vice President of Chandler Fab Operations, NXP Semiconductors, are named presenters.
DEC
12
SAT
–
DEC
16
WED
IEEE International Electron Devices Meeting (IEDM) · San Francisco (San Francisco Bay Area), CA
Electronics · SemiconductorsThe program covers semiconductor and electronic device technology, design, manufacturing, physics, modeling, and emerging computing architectures. It includes keynote presentations, technical paper sessions, tutorials, short courses, industry panels, and exhibits. Keynotes address “AI Driven Semiconductor Paradigm Shift: Optimizing the Semiconductor Industry from Device Scaling to System Integration,” “Driving AI Memory Innovation: From Device Technology to AI Memory Platform,” and “Technology Trends in the IDM Semiconductor Business.” Tutorials cover transistor evolution from planar devices to nanosheets and beyond; chiplets, heterogeneous integration, and 3D stacking; memory technologies and system co-optimization in the AI era; AI in physics-based semiconductor modeling; diverse memory technologies for adaptive computing; and advanced optical devices and wafer-scale assembly for co-packaged optics and optical I/O. The short-course program addresses distributed network design for AI, angstrom-era logic scaling, edge-device performance and design-technology/system-technology co-optimization, atomic-layer processing, advanced-packaging reliability, cryogenic electronics, memory-centric computing, HBM, oxide-semiconductor-channel DRAM, NAND scaling, spintronics, and chiplet and advanced-packaging technologies for AI and HPC systems.
FEB
14
SUN
–
FEB
18
THU
IEEE International Solid-State Circuits Conference (ISSCC) · San Francisco (San Francisco Bay Area), CA
Data Centers & Cloud · Electronics · SemiconductorsSponsored by IEEE and SSCS, the conference is a global forum for advances in solid-state circuits and systems-on-a-chip. The 2027 program centers on “Trusted Sustainable Silicon Intelligence from Edge to Cloud,” with parallel technical paper presentations, invited industry sessions, demonstrations, tutorials, Advanced-Circuit-Design Forums, a Student Research Preview, and a hardware-security short course. Plenary talks include “Holistic Semiconductor Lithography for the Age of AI” by Marco Pieters, Executive Vice President and Chief Technology Officer, ASML; “The Next Leap in Image Sensors: Pixels and Beyond in the AI Era” by Yusuke Oike, CTO / Senior Vice President, R&D, Sony Semiconductor Solutions; “At the End of the Copper Tunnel, There Is Light” by Matt Murphy, Chairman and CEO, Marvell; and “From Silicon to Deployed Infrastructure: Redefining the Semiconductor Design Challenge at Hyperscale” by Rani Borkar, President, Azure Hardware Systems and Infrastructure, Microsoft. Forums cover next-generation AI and HPC through memory, interconnect, power, and architecture co-design; 448G–3.2T wireline data converters; electrical and optical connectivity; AI-optimized sensing; 6G circuits and systems; and silicon systems for quantum sensing and computing. Tutorials address safe robotics, switched-capacitor power converters, adaptive clocking, time-domain ADCs, machine-learning accelerator design, energy-harvesting sensing, mm-wave LO scaling, analog design automation, radar LO generation, and die-to-die interfaces. The hardware-security short course covers fundamentals, cryptographic architectures, hardware attacks and chip-level countermeasures, and hardware roots of trust. Industry-focused sessions address commercial chip-product releases and topics including processors/SoCs, AI, machine learning, 5G, radar, wireline, quantum computing, automotive, healthcare, and robotics. The program also includes the panel “The Analog Renaissance: Can Unconventional Physical Computing and Optical Interconnects Define the Next Strategic Leap?”
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