72nd Annual IEEE International Electron Devices Meeting
Date
December 12
Format
Hybrid
Location
San Francisco, CA
Price
Regular conference rates; IEEE member, non-member, student, and life-member tiers. Discounted rates are available through November 10, 2026.
Importance:
Editions
About
The technical program covers semiconductor and electronic-device technology, design, manufacturing, physics, and modeling, including CMOS transistor technology, advanced memory, displays, sensors, MEMS, quantum and nanoscale devices, optoelectronics, power and energy-harvesting devices, and emerging material systems. Featured technical themes include AI-driven semiconductor scaling and system integration; memory technologies and system co-optimization; IDM manufacturing trends; chiplets, heterogeneous integration, and 3D stacking; AI and machine learning in physics-based semiconductor modeling; advanced-packaging reliability; cryogenic electronics for quantum computing; and optical devices for co-packaged optics and optical I/O. Short-course subjects include AI-era logic scaling, atomic-layer processing, HBM, NAND, spintronics, and memory-centric computing.
Schedule
Times are local to the event.
1:30 PM – 2:50 PM2 sessions at the same time
1:30 PM – 2:50 PM
Chiplet, heterogeneous integration, 3D stacking technologies principles and state of the art
3:05 PM – 4:25 PM2 sessions at the same time
3:05 PM – 4:25 PM
Memory Technologies and System Co-Optimization in the AI Era: Past, Present and Future
3:05 PM – 4:25 PM
AI in Physics-based Semiconductor Modeling: From PDE-constrained Learning to Agentic TCAD/DTCO Workflows
4:40 PM – 6:00 PM2 sessions at the same time
4:40 PM – 6:00 PM
Diverse Memory Technologies for Adaptive Computing: From Device Physics to Cooperative Architectures
4:40 PM – 6:00 PM
Advanced Optical Devices and Wafer-Scale Assembly for next-generation CPO and Optical I/O
Speakers(22)
Executive Vice President – Chief Technology and Operations Officer – General Manager, Intel Foundry
Vice President of Device Technology Solution, SK Hynix
President, Quality, Manufacturing & Technology, STMicroelectronics
Senior Director, Silicon Design Engineering, AMD
Director, Process Integration R&D, ST Micro
Executive Director of R&D Engineering, Synopsys
Intel Fellow
Fellow, Silicon Photonics, imec
AMD Fellow
LAM Executive
Research Director, Université Paris-Saclay CNRS
Distinguished Engineer, SK hynix
Senior Fellow, CEA-Leti
Principal Engineer, Intel
Senior Director, Qualcomm
Deputy Director, TSMC
IC Design Engineer, Google
Chief Specialist, Kioxia
Distinguished Member of Technical Staff, Micron
Distinguished Member of Technical Staff, Micron
Professor, Tohoku University
Distinguished Engineer, IBM
Funding programs
Find open federal and state grants, loans, tax credits and other programs relevant to this event and the people you'll meet there, including programs in other states if you're weighing where to build.
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